The present invention relates to a combined type semiconductor memory module, and in particular to a DRAM refresh method.
A list of documents referred to herein is as follows. The documents will be referred to by using a document number.
Document 1: LRS1337 Stacked Chip 32M Flash Memory and 4M SRAM Data Sheet (retrieved on Apr. 21, 2000), Internet <URL:http://www.sharpsma.com/index.html>
Document 2: JP-A-11-219984 (laid open in Aug. 10, 1998) (corresponding to U.S. Pat. No. 6,157,080 published in Dec. 5, 2000)
Document 3: JP-A-5-299616 (laid open in Nov. 12, 1993) (corresponding to EUROPEAN PATENT APPLICATION Publication number 566,306 laid open in Oct. 20, 1993)
Document 4: JP-A-8-305680 (laid open in Nov. 22, 1996)
Document 5: JP-A-11-204721 (laid open in Jul. 30, 1999)
Document 6: JP-A-10-11348 (laid open in Jan. 26, 1998)
In the document 1, there is described a combined type semiconductor memory module including a flash memory and an SRAM sealed integrally with a BGA (ball grid array) type package by using a stacked chip configuration. The flash memory and the SRAM share address input terminals and data input and output terminals with respect to input and output electrodes of an FBGA (Fine-pitch Ball Grid Array) type package. However, they have independent control terminals, respectively.
In the document 2, there is described a combined type semiconductor memory module including a flash memory and an SRAM integrally sealed to a BGA (ball grid array) type package by using a stacked chip. Signal pads of the flash memory are subject to face down bonding to a circuit substrate of the BGA package via solder bumps. Signal pads of the SRAM mounted on the flash memory are connected to the substrate by wire bonding.
With reference to FIG. 17 of the document 3, there is described a combined type semiconductor memory module including a flash memory chip and a DRAM chip integrally sealed to a lead frame type package. Furthermore, with reference to FIG. 1, there is described such a flash memory and a DRAM that address input terminals, data input and output terminals, and control terminals are shared for inputting and outputting with respect to input and output electrodes of the package.
In the document 4, there is described a semiconductor device. In this semiconductor device, an SRAM chip is mounted on a die pad. On the SRAM chip, a flash memory chip and a microcomputer chip connected via a bump electrode are mounted. Those chips are sealed integrally with a lead terminal type package to form the semiconductor device.
With reference to FIG. 15 of the document 5, there is described such a semiconductor device that two small-sized chips are mounted on the back of one large-sized chip via an insulation plate and those chips are integrally sealed to a lead frame type package. It is described that there are a flash memory chip, a DRAM chip, and an ASIC (Application Specific IC) as a combination of chips that can be mounted and consequently a memory embedded logic LSI is implemented by one package.
In the document 6, there is described a technique for avoiding collision between access from the outside and refresh of the DRAM by providing two DRAM blocks, storing the same data in duplicate, and staggering two DRAM blocks in refresh timing. This control is conducted by a DRAM controller. This DRAM controller issues physically independent address signals and control signals to the two DRAM blocks.